Newer integrated circuit products have stringent power and performance requirements. For example, there is an almost constant drive in the industry toward using lower voltages in order to minimize the power required to operate a chip. Chip design considerations must include factors associated with technology data, like the allowed operating voltage range of each library element, the transient noise sensitivity of circuit functionality to transient power supply noise, etc., and factors associated with product data, like the power-supply voltage tolerances, the selected package type and size, etc.
One particular area of variability in circuit design is the use of decoupling capacitors. On-chip decoupling capacitors (commonly referred to as “decaps”) are typically used to prevent noise-related circuit degradation. More specifically, in advanced electronic computing systems, the decoupling capacitors serve as a charge reservoir to support instantaneous current surges that accompany simultaneous circuit switching. The decoupling capacitors are recharged by the external power supply, but the time-varying nature of the recharge/discharge process creates undesirable variation in the on-chip power-supply voltage. Generally speaking, the magnitude of the voltage variation can be reduced by adding more decoupling capacitors. Constraining the voltage variation is advantageous because it restricts the “voltage loss” between the power supply and the on-chip circuits. If a particular minimum circuit voltage is required to achieve a specified level of circuit performance, a reduction in voltage variation permits the use of lower power-supply voltages. This, in turn, reduces power consumption.
Decoupling capacitors may be employed on chip and across all levels of packaging, including single chip and multi chip modules, boards and back planes. The number of decoupling capacitors in a circuit design can be increased to reduce the amount of transient power supply noise; however, this noise reduction comes at the cost of the larger physical area required to accommodate the increased number of decoupling capacitors. There is no current methodology for reliably managing the performance, power-supply noise, die area, and power trade-offs while optimizing cost in a circuit design.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.